1. Field of the Invention
The invention relates generally to semiconductor devices having trench type capacitors, and more particularly, to a high integration density trench-type capacitor structure for semiconductor devices and a manufacturing method therefor. The invention has particular applicability to high density dynamic random access memory integrated circuits.
2. Description of the Prior Art
A dynamic semiconductor memory device has been already well known. FIG. 1 is a block diagram showing an entire structure of such a conventional dynamic semiconductor memory device.
In FIG. 1, the dynamic semiconductor memory device comprises an array including a plurality of memory cells each serving as a memory portion, a row decoder and a column decoder for selecting addresses thereof, and an input/output interface portion including sense amplifiers connected to an input/output buffer. The plurality of memory cells are connected to intersections of word lines connected to the row decoder and bit lines connected to the column decoder, respectively, the word lines and the bit lines constituting a matrix. In the above described manner, the above described array is structured.
Operation is now described. A memory cell connected to an intersection of each of the word lines and each of the bit lines selected by the row decoder and the column decoder in response to a row address signal and a column address signal externally applied. Information is read out or written from or to the memory cell through the input/output interface portion including the sense amplifiers and the input/output buffer.
Each bit line is connected to the sense amplifier, an amplifier of a flip-flop type, and a signal fed out from the memory cell is amplified by this amplifier. As a level of the fed out signal is very low, a high sensitive amplifier is required.
FIG. 2 is a schematic diagram showing a periphery of the sense amplifier. The sense amplifier compares an output signal from the memory cell with a prescribed reference voltage and amplifies the difference between them. Bit lines are connected to either side of the sense amplifier. One bit line is connected to memory cells, the other is connected to dummy cells. A read out signal from the dummy cell is used as a reference voltage. Each one dummy cell is coupled to either side of the sense amplifier. Output voltage from the dummy cell is set to be a midway value between a high level signal and a low level signal fed from the memory cell. In order to enable above, storage capacitor of the dummy cell is made to be a half of that of the memory cell. In order to amplify the output signal from the memory cell efficiently, each bit line is charged to a certain precharge level V.sub.P (usually corresponding to a supply voltage or one half of the supply voltage) while data is kept in the memory cell.
FIG. 3 is an equivalent circuit explaining a voltage difference to be sensed by the sense amplifier. In the drawing, C.sub.B is a capacitance value of the bit line and C.sub.S is a capacitance value of one memory capacitor. T.sub.R is a select gate transistor to select a memory cell located at the junction of the selected bit line and the selected word line.
A read out operation when the memory capacitor is kept at high level is as follows. A voltage of the bit line is set to be a precharge level. Before the select gate transistor is turned on, the charge on the memory cell capacitor is C.sub.S .multidot.V.sub.H, and the charge on the bit line capacitor is C.sub.B .multidot.V.sub.P. Where, V.sub.H is high level voltage. And V.sub.P is a precharge level voltage. As a total charge stored is reserved, the charge after the select gate transistor is turned on is as follows. EQU Q=(C.sub.B +C.sub.S).multidot.V.sub.P' =C.sub.S .multidot.V.sub.H +C.sub.B .multidot.V.sub.p ( 1)
where V.sub.p' , is a new level satisfying an equation (1) ##EQU1## As shown in equation (2), a voltage of the bit line changes by .DELTA.V.sub.H. The sense amplifier detects the voltage difference .DELTA.V.sub.H.
Same is true in the case that the memory cell is kept at low level. ##EQU2## In this case, a voltage of the bit line changes by .DELTA.V.sub.L and the sense amplifier detects the voltage difference .DELTA.V.sub.L.
On the other hand, before the read out operation, a voltage of the dummy cell is always kept at low level V.sub.L and a bit line connected to the dummy cell is kept at a precharge level. Therefore, when the select gate transistor is turned on, a voltage of the bit line is lowered by .DELTA.V.sub.D, a voltage difference satisfying an equation (4), from the precharge level V.sub.P. ##EQU3## where C.sub.D is a capacitance value of the dummy cell.
FIG. 4 is a schematic diagram showing the relationship between high level, low level and prescribed midway value of the dummy cell.
When a certain memory cell and a corresponding dummy cell is selected, a voltage of a bit line changes from a precharge voltage V.sub.P depending on a magnitude of a read out signal from the memory cell and the dummy cell. A difference between the precharge voltage V.sub.P and the voltage after the select gate transistor is turned on is fed to the sense amplifier to work.
A minor signal read out from the memory cell to the bit line is amplified by the sense amplifier. As an output terminal is used as an input terminal as well, amplified signal is rewritten to the read out memory cell via the bit line automatically. Therefore, when a data signal is read out from a certain memory cell, the data is automatically rewritten in the same memory cell. A dynamic RAM keeps information charges by storing charges on the capacitors. If the data signal is not rewritten periodically, the data will be dissipated. The sense amplifier keeps on rewriting the data to the memory cells and prevents the data from dissipating by above described function. The function is called "refreshing".
As to the detail operation of the dynamic RAM, U.S. Pat. No. 3,940,747, entitled "High Density, High Speed Random Access Read-Write Memory" can be referred to
Conventionally, two kinds of semiconductor memory devices have been known as a dynamic semiconductor memory device of a trench type for high integration density of more than 4M bits, which is described by Chatterjee et al. in IEDM (International Electron Device Meeting) Technical Digest.
The two kinds of dynamic semiconductor memory devices comprise a type in which charges are stored on the side of a semiconductor substrate in a capacitor cell portion and a type in which charges are stored in a semiconductor layer formed on the semiconductor substrate through an insulating film.
FIG. 5 is a cross sectional view showing main portions of the former type. Referring to FIG. 5, a trench 2 which is a concave portion is formed in a P.sup.- type semiconductor substrate 1. An N.sup.+ type charge storage region 3 in which charges are to be stored for storing information is formed on the surface of the trench 2. A first insulating layer 4 is formed on the inner peripheral surface of the trench 2 and a part of the upper surface of the semiconductor substrate 1. A capacitor electrode 5 connected to a power supply V.sub.CC is formed on the first insulating layer 4. In this case, the above described charge storage region 3, the first insulating layer 4 and the capacitor electrode 5 constitute a capacitor cell portion of the semiconductor memory device.
A first N.sup.30 type source/drain region 6 is formed along the upper surface of the semiconductor substrate 1, one end thereof being electrically connected to the above described charge storage region 3. In addition, a second N.sup.+ type source/drain region 7 is formed opposed to the first source/drain region 6, on the semiconductor substrate 1. A third insulating layer 8 is formed on a channel region interposed between the source/drain regions 6 and 7. A gate electrode 9 serving as a word line is formed on the third insulating layer 8. The word line is shown to extend in the vertical direction in FIG. 5. The semiconductor substrate 1, the source/drain regions 6 and 7, the third insulating layer 8 and the gate electrode 9 constitute a transfer gate portion.
Furthermore, a bit line 10 extends upward from the second source/drain region 7. The bit line 10 is connected to a sense amplifier (not shown). In FIG. 5, numeral 11 denotes a P.sup.+ type region for protecting the charge storage region 3, numeral 12 denotes a P.sup.+ type region for protecting inversion and parasitic capacitance numeral 13 denotes an isolation insulating film for isolation formed on the P.sup.+ type region 12, and numeral 27 denotes an interlayer insulating layer.
In the semiconductor memory device, the second source/drain region 7 connected to the bit line 10 is held in advance at a particular intermediate potential by a function of a sense amplifier. When a potential on the word line, i.e., of the gate electrode 9 is higher than a threshold voltage of the transfer gate, the channel region serving as an N type inversion layer is formed on the semiconductor substrate 1 immediately under the gate electrode 9. As a result, conduction between the source/drain regions 6 and 7 occurs. In this case, if and when memory information stored in a memory cell is "0", that is, electrons are stored in the charge storage region 3, conduction between the source/drain regions 6 and 7 occurs. As a result, a potential of the second source/drain region 7 which has been held so far at the intermediate potential is decreased, so that a potential on the bit line 10 is decreased. On the other hand, when memory information stored in the memory cell is "1", that is, electrons are not stored in the charge storage region 3, the potential on the second source/drain region 7 which has been held at the intermediate potential is increased. As a result, the potential on the bit line 10 is increased. The change is potential on the bit line 10 is sensed and amplified by a sense amplifier. Consequently, the memory information is extracted. At the same time, the same memory information is refreshed. The same memory information is rewritten again to the memory cell within the same cycle.
Additionally, FIG. 6 is a diagram showing the latter example, in which charges are stored in a semiconductor layer formed separated by the semiconductor substrate 1 and the insulating film. In FIG. 6, a charge storage region 14 which is an N.sup.+ type semiconductor layer is formed inside the trench 2 of the semiconductor substrate 1 and on a part of the upper surface of the semiconductor substrate 1 through the insulating layer 4. The first source/drain region 6 and a charge storage region 14 are electrically connected on the upper surface of the semiconductor substrate 1. The power supply V.sub.CC is connected to the semiconductor substrate 1. The semiconductor substrate 1 serves as a capacitor electrode 15 in the capacitor cell portion. The other structure is the same as that of the semiconductor memory device shown in FIG. 5. The same portions have the same reference numerals and hence, descriptions thereof are omitted.
In the semiconductor memory device, charges are stored in the charge storage region 14 inside the trench 2. The stored charges are carried to the second source/drain region 7 connected to the bit line 10 through the first source/drain region 6 and the channel formed in the transfer gate portion.
Furthermore, an improved one of the above described semiconductor memory device shown in FIG. 6 is described in IEDM Technical Digest, 1984. The semiconductor memory device is referred to as an IVEC (Isolation-Merged Vertical Capacitor Cell). FIG. 7 is a cross sectional view showing main portions of the semiconductor memory device. In FIG. 7, the device comprises two capacitor cells in a single trench 2. More specifically, charge storage regions 16 which are N.sup.+ type semiconductor layers are provided along the walls on both sides of the trench 2 through an insulating layer 4, respectively. A capacitor electrode 17 is formed to be interposed between the charge storage regions 16 through fourth insulating layers 18. A power supply V.sub.CC is connected to the capacitor electrode 17. In addition, the charge storage regions 16 are electrically connected to first source/drain regions 6 in transfer gate portions, in the upper ends of the walls on both sides of the trench 2. The charge storage regions 16 and the first source/drain regions 6 are connected to each other on the sidewalls of the trench 2 for the following reason. The area occupied by the first source/drain regions 6 in the upper surface of the semiconductor substrate 1 can be decreased, as compared with the case in which the charge storage regions 16 and the first source/drain regions 6 are connected to each other on the upper surface of the semiconductor substrate 1. As a result, a semiconductor memory device having high integration density can be obtained. In FIG. 7, numeral 19 denotes an interlayer insulating layer. The other structure is the same as that of the above described semiconductor memory device shown in FIG. 6. The same portions have the same reference numerals and hence, descriptions thereof are omitted.
In the semiconductor memory device, charges are stored in the charge storage regions 18 in the trench 2. The stored charges are carried to the second source/drain regions 7 connected to a bit line 10 through the first source/drain regions 6 and channels formed in the transfer gate portions.
Similarly, a developed one of the semiconductor memory device shown in FIG. 6 is disclosed in Japanese Patent Laying-Open Gazette No. 3260/1983. FIG. 8 is a cross sectional view showing main portions of the memory device. In FIG. 8, the device comprises a P type semiconductor substrate 1 having a trench 2 formed therein, a capacitor and a transfer gate. The capacitor comprises a charge storage layer 20, an insulating film 21 and a capacitor electrode 22 formed in the trench.
Charges stored in the charge storage layer 20 is carried to a bit line 10 through one N type source/drain region 6 connected to the charge storage layer 20, a channel formed under a gate electrode 9 and the other N type source/drain region 7.
A developed one of the semiconductor memory device shown in FIG. 6 is described in IEDM Technical Digest, 1986. The semiconductor memory device is referred to as a Dielectrically Encapsulated Trench Capacitor Cell. FIG. 9 is a cross sectional view showing main portions of the semiconductor memory device. In FIG. 9, the device comprises a P type semiconductor substrate 1 having a trench formed therein, a capacitor and a transfer gate. The capacitor includes a capacitor electrode comprising the semiconductor substrate 1 and a P.sup.+ type semiconductor layer 11 and a capacitor insulating film comprising a thin insulating film 4 interposed therebetween. An N type semiconductor layer 14 is a charge storage region.
Charges stored in the charge storage region 14 is carried to one N type source/drain region 6 through an N type semiconductor layer 30. Charges carried in the one source/drain region 6 is carried to the other source/drain region 7 through a transfer gate comprising a gate insulating film 8 and an electrode 9. The other structure is the same as that shown in FIG. 5. The same portions have the same reference numerals and hence, descriptions thereof are omitted.
However, the conventional semiconductor memory device shown in FIG. 5 has the following problems. A minority carrier in the semiconductor substrate 1 induced by alpha rays of a radioactive element included in a package or the like tends to be collected in the peripheral region of the trench 2. As a result, a potential of the charge storage region 3 is changed, so that a malfunction, that is, soft errors of the semiconductor memory device occurs. On the other hand, when the semiconductor memory device is made fine, spacing between the trench 2 and an adjacent trench is decreased.
A depletion layer provided between the charge storage region 3 on the surface of the trench 2 and the semiconductor substrate 1 expands to a depletion layer provided between a charge storage region on the surface of the adjacent trench and the semiconductor substrate 1. As a result, the depletion layers interfere with each other, so that the potential of the charge storage region 3 is changed, resulting in a malfunction.
FIG. 10 is a drawing explaining the malfunction caused by a depletion layer.
When a memory cell A is high and a memory cell B is low (electrons are charged), p-n junction between the N.sup.+ type layer 3a and P type substrate 1 is reversely biased in the memory cell at high level and a depletion layer expands toward the memory cell B. If the depletion layer of memory cell A reaches to that of memory cell B, electric field of the cell A reaches to the cell B, thereby charges stored in the cell B fled to the cell A and a state of the cell B changes from a low level to a high level. As a result, the memory cell works erroneously.
In the semiconductor memory device shown in FIG. 6, the charge storage region 14 is provided in the trench 2 of the semiconductor substrate 1. Since the charge storage region 14 is electrically isolated from the semiconductor substrate 1 through the first insulating layer 4, a potential of the charge storage region 14 is not changed by a minority carried in the semiconductor substrate 1 induced by alpha rays. As a result, the semiconductor memory device has some advantages. More specifically, soft errors can be prevented and interference between the adjacent charge storage regions 14 can be prevented. In addition, integration density of the semiconductor memory device can be increased. However, a potential of the semiconductor substrate 1, i.e., the capacitor electrode 15 is changed by charging and discharging a circuit of the semiconductor memory device, because the semiconductor substrate 1 operates as the capacitor electrode 15 in the capacitor cell portion. Thus, a potential of the charge storage region 14 is changed. As a result, the semiconductor memory device erroneously operates.
In the semiconductor memory device shown in FIG. 7, soft errors can be avoided and integration density can be increased, as in the semiconductor memory device shown in FIG. 6. The reason is that the charge storage regions 16 are isolated from the semiconductor substrate 1 through the insulating layers 4. On the other hand, the semiconductor memory device has the capacitor electrode 17 in the trench 2. Thus, even if a potential of the semiconductor substrate 1 is changed by charging and discharging the circuit, potentials of the charge storage regions 16 do not change.
FIG. 11 is a drawing showing a capacitance coupling between a bit line and a substrate.
Charges stored in a charge storage layer 4 is represented as follows. EQU Q.sub.N =C (V.sub.C -V.sub.S) (5)
where
V.sub.C : voltage at a capacitor electrode
V.sub.S : voltage at a charge storage layer. There is a large capacitance coupling between a substrate and a bit line as shown in the drawing. Therefore, when the voltage of the bit line is changed due to charging or discharging, the capacitance coupling makes the voltage of the substrate change to V.sub.C'. Hence a voltage of the capacitor electrode changes from a prescribed value if a memory cell has the structure shown in FIG. 11.
When a data signal is stored in the above described memory cell, charges stored change as shown in equation (5) EQU Q=C (V.sub.C' -V.sub.S) (6)
Q is not the same as Q.sub.N. The read out data is not correct.
On the contrary, in the case of a memory cell structured as shown in FIG. 7, as the capacitor electrode is separated from the substrate by an insulating layer, the voltage of the capacitor electrode does not change. Therefore charges stored on the charge storage layer does not change and a constant read out voltage can be obtained. As a result, a malfunction of the semiconductor memory device can be prevented. However, a capacitor portion corresponding to a single memory cell is provided only on the side of one side surface of the trench 2 as a single charge storage region 16. Thus, capacitance of a capacitor is decreased. Consequently, a potential which appears on the bit line 10 is not changed so much, a malfunction of a sense amplifier is liable to occur. Furthermore, there is the following problem in the manufacturing process. It is very difficult to form three chambers in the trench 2 and form therein the charge storage regions 16 and the capacitor electrode 17 with accuracy.
In the semiconductor memory device shown in FIG. 8, the charge storage region 20 is electrically isolated from the semiconductor substrate 1 through the insulating layer 2, as in the memory device shown in FIGS. 6. Consequently, soft errors due to alpha rays can be prevented. Since interference between the adjacent charge storage regions 20 can be prevented, integration density of the semiconductor memory device is increased.
However, a contacting portion of the charge storage region 20 and the N.sup.+ impurity region 6 on the semiconductor substrate is formed on the planar surface. Thus, constant spacing is required between the transfer gate 9 and the charge storage region 20. As a result, it is difficult to increase integration density of the semiconductor memory device.
In the semiconductor memory device shown in FIG. 9, the charge storage region 4 is electrically isolated from the substrate through the insulating layer 4, as in the memory device shown in FIG. 6. As a result, the semiconductor memory device has the following advantages. More specifically, soft errors caused by alpha rays can be prevented. Since interference between the adjacent charge storage regions 4 can be prevented, integration density can be increased. P type impurities having a high concentration of the capacitor electrode 11 is interrupted by the insulating film 4, so that the impurities do not diffuse into the channel region under the transfer gate 9.
However, as in the device shown in FIG. 6, a potential of the semiconductor substrate 1, i.e., the capacitor electrode is changed by charging and discharging the circuit of the semiconductor memory device. Therefore, the amount of charges stored in the charge storage region 4 changes. As a result, the semiconductor memory device erroneously operates.